1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device having a normal mode and a power down mode.
2. Description of the Background Art
In a semiconductor memory device referred to as a DRAM (Dynamic Random Access Memory), a refresh operation is carried out to maintain the data stored in a memory cell. This refresh operation is carried out on the basis of a word line. Upon application of a pulse to a selected word line, a read out of small signals, amplify, and rewrite operation are carried out for all the memory cells on the selected word line, whereby all the memory cells on the word line are refreshed at the same time. By sequentially selecting a word line in such a manner, all the memory cells will be refreshed. The method of executing a refresh operation includes the method of carrying out a refresh operation of one cycle (one word line) for every predetermined interval, and the method of refreshing all the memory cells at a burst at an elapse of a predetermined time.
During the execution of such a refresh operation, not only circuitry required for the refresh operation, but also circuitry irrelevant to the refresh operation operates. Therefore, leakage current is generated in association with activation of the transistors included in the circuitry that is not required for the refresh operation. This leakage current becomes so great as to reduce the threshold value of the transistor. Although the threshold value must be lowered in accordance with microminiaturization of the transistor, the entire current consumption of circuitry that uses such a transistor will increase.
An object of the present invention is to provide a semiconductor memory device that can reduce current consumption during a self refresh operation.
According to an aspect of the present invention, a semiconductor memory device with a normal mode and a power down mode includes a plurality of memory cells, a plurality of first word lines, a plurality of bit line pairs, a sense amplifier, an address buffer, a self refresh control circuit, a row decoder, a plurality of first word line drivers, a first power supply, and a second power supply. The plurality of memory cells are arranged in rows and columns. The plurality of first word lines are arranged in rows. The plurality of bit line pairs are arranged in columns. The sense amplifier amplifies the data signal of the plurality of bit line pairs. The address buffer generates an internal address signal in response to an external address signal. The self refresh control circuit generates a refresh address signal when in a power down mode. The row decoder responds to an internal address signal to generate a decode signal when in a normal mode, and responds to a refresh address signal to generate a decode signal when in a power down mode. The plurality of first word line drivers are provided corresponding to the plurality of first word lines to render a corresponding first word line active in response to a decode signal. The first power supply supplies a power supply voltage to the sense amplifier, the address buffer, the self refresh control circuit, the row decoder, and the plurality of first word line drivers when in a normal mode, and does not supply a power supply voltage to the sense amplifier, the address buffer, the self refresh control circuit, the row decoder, and the plurality of first word line drivers when in a power down mode. The second power supply provides a power supply voltage to the sense amplifier, the self refresh control circuit, the row decoder, and the plurality of first word line drivers when in a power down mode, and does not supply of a power supply voltage to the sense amplifier, the self refresh control circuit, the row decoder and the plurality of first word line drivers when in a normal mode.
In the above semiconductor memory device, power consumption during a self refresh operation can be reduced since power is not supplied to the address buffer that is not required for the self refresh operation when in a power down mode.
According to another aspect of the present invention, a semiconductor memory device that has a normal mode and a power down mode includes a main power supply line, a main ground line, first and second sub-power supply lines, first and second sub-ground lines, a plurality of memory cells, a plurality of first word lines, a plurality of bit line pairs, a sense amplifier, an address buffer, a self refresh control circuit, a row decoder, a plurality of first word line drivers, a first connection circuit, a second connection circuit, a third connection circuit and a fourth connection circuit. The main power supply line receives a power supply voltage. The main ground line receives a ground voltage. The plurality of memory cells are arranged in rows and columns. The plurality of first word lines are arranged in rows. The plurality of bit line pairs are arranged in columns. The sense amplifier amplifies the data signal of the plurality of bit line pairs. The address buffer generates an internal address signal in response to an external address signal. The self refresh control circuit generates a refresh address signal when in a power down mode. The row decoder generates a decode signal in response to an internal address signal when in a normal mode and in response to a refresh address signal when in a power down mode. The plurality of first word line drivers are provided corresponding to the plurality of first word lines to render a corresponding first word line active in response to a decode signal. The first connection circuit sets the main power supply line and the first sub-power supply line connected and unconnected when in a normal mode and in a power down mode, respectively. The second connection circuit sets the main ground line and the first sub-ground line connected and unconnected when in a normal mode and in a power down mode, respectively. The third connection circuit sets the main power supply line and the second sub-power supply line connected and unconnected when in a power down mode and in a normal mode, respectively. The fourth connection circuit sets the main ground line and the second sub-ground line connected and unconnected when in a power down mode and in a normal mode, respectively. The address buffer includes a plurality of first logic circuits and a plurality of second logic circuits. The plurality of first logic circuits are connected between the main power supply line and the first sub-ground line to output a signal of a high logic level when in a power down mode. The plurality of second logic circuits are connected between the first sub-power supply line and the main ground line to output a signal of a low logic level when in a power down mode. The self refresh control circuit includes a plurality of third logic circuits, and a plurality of fourth logic circuits. The plurality of third logic circuits are connected between the main power supply line and the second sub-ground line to output a signal of a high logic level when in a normal mode. The plurality of fourth logic circuits are connected between the second sub-power supply line and the main ground line to output a signal of a low logic level when in a normal mode.
In the above semiconductor memory device, the address buffer does not operate when in a power down mode. Therefore, the subthreshold current flowing through the plurality of first and second logic circuits can be reduced by setting the main power supply line and the first sub-power supply line unconnected and the main ground line and the first sub-ground line unconnected by the first and second connection circuits, respectively. In a normal mode, the self refresh control circuit does not operate. Therefore, the subthreshold current flowing through the plurality of third and fourth logic circuits can be reduced by setting the main power supply line and the second sub-power supply line unconnected and the main ground line and the second sub-ground line unconnected by the third and fourth connection circuits, respectively.
According to a further aspect of the present invention, a semiconductor memory device having a normal mode and a power down mode includes a logic unit with a plurality of logic circuit groups, and a DRAM unit. The DRAM unit includes a plurality of memory cells, a plurality of first word lines, a plurality of bit line pairs, a sense amplifier, an address buffer, a self refresh control circuit, a row decoder, and a plurality of first word line drivers. The plurality of memory cells are arranged in rows and columns. The plurality of first word lines are arranged in rows. The plurality of bit line pairs are arranged in columns. The sense amplifier amplifies the data signal of the plurality of bit line pairs. The address buffer generates an internal address signal in response to an external address signal. The self refresh control circuit generates a refresh address signal when in a power down mode. The row decoder generates a decoded signal in response to an internal address signal and in response to a refresh address signal when in a normal mode and in a power down mode, respectively. The plurality of first word line drivers are provided corresponding to the plurality of first word lines to render a corresponding first word line active in response to a decoded signal.
The semiconductor memory device further includes a first power supply, a second power supply, and a temporary save circuit. The first power supply supplies a power supply voltage to the logic unit, the sense amplifier, the address buffer, the self refresh control circuit, the row decoder, and the plurality of first word line drivers when in a normal mode, and does not supply a power supply voltage to the logic unit, the sense amplifier, the address buffer, the self refresh control circuit, the row decoder, and the plurality of first word line drivers when in a power down mode. The second power supply supplies a power supply voltage to the sense amplifier, the self refresh control circuit, the row decoder and the plurality of first word line drivers when in a power down mode, and does not supply a power supply voltage to the sense amplifier, the self refresh control circuit, the row decoder, and the plurality of first word line drivers when in a normal mode. The temporary save circuit temporarily saves the data of the plurality of logic circuit groups into the DRAM unit before a power down mode is entered.
The semiconductor memory device does not have the data in the logic unit lost even when power is not supplied to the logic unit during a power down mode.